By Yuan Xie (auth.), Yuan Xie (eds.)
This publication explores the layout implications of rising, non-volatile reminiscence (NVM) applied sciences on destiny machine reminiscence hierarchy structure designs. in view that NVM applied sciences mix the rate of SRAM, the density of DRAM, and the non-volatility of Flash reminiscence, they're very beautiful because the foundation for destiny common thoughts. This e-book presents a holistic viewpoint at the subject, masking modeling, layout, structure and functions. the sensible details incorporated during this publication will permit designers to use rising reminiscence applied sciences to enhance considerably the performance/power/reliability of destiny, mainstream built-in circuits.
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Extra info for Emerging Memory Technologies: Design, Architecture, and Applications
2008). Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. Proceedings of the Design Automation Conference (pp. 554–559). 7. , et al. (2009). PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM. Proceedings of the International Conference on, Computer-Aided Design (pp. 269–275). 8. Evans, R. , & Franzon, P. D. (1995). Energy consumption modeling and optimization for SRAM’s. IEEE Journal of Solid-State Circuits, 30(5), 571–579.
12 Sequential write method: SET-before-RESET Fig. 4 Area Model Since NVSim estimates the performance, energy, and area of non-volatile memory modules, the area model is an essential component of NVSim, especially given the facts that interconnect wires contribute a large portion of total access latency and access energy and the geometry of the module becomes highly important. In this section, we describe the NVSim area model from the memory cell level to the bank level in details. 1 Cell Area Estimation Three types of memory cells are modeled in NVSim: MOS-accessed, cross-point, and NAND string.
IEEE Journal of Solid-State Circuits, 26(4), 525–536. 50 X. Dong et al. 35. , et al. (2011). 2ns read-write random-access time and 160ns MLC-access capability. Proceedings of the IEEE International Solid-State Circuits Conference (pp. 200–201). 36. , et al. (2011). Relaxing non-volatility for fast and energy-efficient STT-RAM caches. Proceedings of the International Symposium on High Performance Computer, Architecture ( pp. 50–61). 37. Sutherland, I. , et al. (1999). Logical effort: designing fast CMOS circuits.
Emerging Memory Technologies: Design, Architecture, and Applications by Yuan Xie (auth.), Yuan Xie (eds.)